WHO WE ARE
CONVOLVE consortium consists of 18 partners from academia and industry with strong complementary competencies in different levels of design hierarchy.
Technische Universiteit Eindhoven (Project Coordinator)
The main role of TU/e is the project coordination (WP9), but also has major contributions in WP3, developing research and design composable real-time platforms and associated modelling, in WP5, on mapping and compiler frameworks that enable integration of the accelerators in the RISC-V platform thereby providing timing guarantees to the running applications, in WP6, working on compositional models for performance analysis, and in WP2, on dynamic reconfigurable CGRA.
Eidgenoessische Technische Hochschule Zuerich
ETHZ’s major contribution is in WP6, supporting the work of a composable SoC template and working with partners to ensure efficient integration of novel accelerators into this template and in WP7 working on the moon-shot demo by supporting IC Design and Test activities.
Friedrich Miescher Institute for Biomedical Research Foundation
FMI’s primary contribution is in WP4 and focuses on developing bio-inspired learning algorithms for continual learning, self-healing, and real-time applications. Additionally, FMI will devise strategies for ephemeral sparsity and sparse neural networks and tailor learning algorithms to the constraints of neuromorphic hardware substrates.
Thales Alenia Space Espanha, SA
Thales’s main role is as WP8 leader with major contributions in WP1 and WP7. For WP8, they lead the tasks about knowledge management and exploitation. Within WP1, Thales takes care of extract and derive to each of the solution development WPs: WP2 – WP5, the requirements for vision applications, especially object and change detection in satellite imagery. In WP7, Thales develops a reconfigurable ML model that filters onboard satellite imagery, and it maps the research into its specific edge application.
Technische Universiteit Delft
TU Delft is leading WP2 and will play a key role in developing reconfigurable ULP accelerators based on emerging technologies and new computing paradigms, which are equipped with self-healing mechanisms. In addition, TU Delft will also have major contributions in WP7 and WP8. In WP7, it will contribute to prototyping and demos, while in WP8 it will contribute to dissemination and technology transfer.
Katholieke Universiteit Leuven
KU Leuven is leading WP6, integrating the WP2/3 modular AI accelerator components into a RISC-V based run-time adaptive processing fabric, which will be taped out in WP7. KU Leuven also develops WP6’s rapid design space exploration framework for optimizing design- and run-time configurability. In WP2, it develops a flexible memory hierarchy for AI accelerators.
Robert Bosch GMBH
Bosch’s major contributions are in WP6 on fault-tolerance and efficiency aspects of DSE framework including instantiation and validation in SoC; in WP1 and WP4 for co-develop acoustic perception algorithms, optimized on dynamism, temporal optimization, and event-based inference; and in WP2 on μ-level optimization of CIM.
NXP Semiconductors Germany GMBH
NXP leads WP7 and contributes to security architecture definition of the developed edge platform, leveraging on its security SoC development expertise. State-of-the-art security topics such as Post Quantum Crypto accelerators for secure execution platforms based on RISC-V architecture shall be researched in the course of the project. NXP, in addition, supports use case partners with requirement gathering, security assessment, incorporating security by design principles & demonstrator development.
GN Store Nord
Their major role is as WP1 leader, where GNA specifies the use case application for speech and audio processing and provides a high-level implementation of such application to the relevant work package. In addition, it establishes the metrics for the test and provides a baseline performance of the current SOTA processors.
RUB is WP3 leader, where it researches and designs highly modular, composable, long term and quantum-secure TEEs for ULP and real-time applications and integration into RISC-V processor architectures. It extends TEE with secure hardware accelerators to achieving ULP long-term security using quantum-secure crypto cores and secure in memory computing based neuromorphic computing.
The University of Manchester
The University of Manchester’s main role is leading WP2 for the development of SNNs for ULP applications. This spans two work packages: in WP4 it investigates and develops the neuromorphic principles used by biological systems to acquire, encode, and process information in an energy efficient manner. In WP2 Manchester’s role is to realize SNNs with low-power accelerators integrated with the RISC-V, first supporting known SNN methods, and expanding to integrate newly developed SNN techniques.
The University of Edinburgh
The University of Edinburgh’s primary role is leading the research in WP5, where it designs the security-aware accelerator-enabling compilation system, the programmer-guided high-level programming environment, and the constraint-aware application search space exploration. Edinburgh also contributes compiler expertise to the design and security assessment of composable secure cores and TEE (WP3) as well as the performance analysis of ML applications and the rapid design of modular architectures, where it ensures effective inter-dependence with the application search-space exploration (WP6).
The PI from Edinburgh is Tobias Grosser.
Universidad de Murcia
UM’s main role is twofold: (1) the identification of constraints and optimization opportunities of the target applications and of the proposed hardware, based on which the compiler is designed (WP5), and (2) the design and implementation of static analysis and transformations that leverage this information to lower general purpose code to the proposed accelerators (WP5).
Universite Internationale de Rabat
UIR’s major contributions are in WP4 in the development of efficient (self-)supervised learning strategies, and resource-efficient neural networks leveraging sparsity, dynamic architectures, and network distillation.
ViNotion’s main role is research on dynamic neural networks (WP4). ViNotion further contributes in WP1 by bringing in the use-case/application of video-based traffic analysis; in WP4 in dynamic NNs; and in WP7 on evaluation and demonstration of the new project technology in the traffic analysis application.
CognitiveIC’s major contribution is to WP3, by developing secure in memory computing based neuromorphic engines that will be protected against fault injection attacks that can be integrated in a RISC-V based TEE.
Axelera AI will work in WP4 developing novel dynamic networks and examine the impact of these and existing networks in WP5 on compiler flow, necessary features to optimally schedule dynamic networks, examining the hardware specs needed to support them and executing dynamic networks on custom hardware.
Confederation of Laboratories for AI Research in Europe
CLAIRE’s main role is in communication and dissemination for the project in WP8, developing the communication and dissemination plan and materials related to these activities, as well as maintaining the project website and social media presence. Further, CLAIRE ensures community engagement and connectivity, while leveraging the existing CLAIRE community, network, and contacts.