EVENTS

This tutorial introduced the ZigZag and Stream frameworks, the SNAX hardware template and the GVSOC simulator. Stream and Zigzag provide opportunities and insights for DNN workload-accelerators spatio-temporal mapping co-optimization across the design space of traditional and In-Memory Computing (IMC) accelerator architectures.

We also dove into the architecture model to help Convolve partners model their accelerator architecture. SNAX is a versatile shell designed to streamline the integration of accelerators into the PULP System-on-Chip (SoC) platform.

Said Hamdioui, head of Computer Engineering Laboratory at Delft University of Technology and co-founder and CEO of Cognitive-IC presented a keynote at LATS24.

The talk provides the edge computing challenges CONVOLVE is addressing, shows the directions, and present some results. It discusses today’s chip technology and computer hardware/architectures (which enable the design of ICT systems), and highlights their limitations making them unsuitable to enable energy efficient solutions needed; not only to minimize the ICT’s electricity consumption and ensure the sustainability, but also to enable many emerging energy-constrained applications such as edge-AI.

The talk covers both the device as well as the architecture aspects. Thereafter, the talk covers some future directions for energy efficient computing that CONVOLVE addresses, while focusing on Computation-In-Memory (CIM) architecture using memsitor devices and inspired with the brain. The huge potential of CIM (in realizing over 100X improvement in terms of energy efficiency) is illustrated based on some real case studies, supported by data measurement of chip prototypes. Aspects related to design, test and reliability of such brain-inspired CIM architectures will be discussed. Future challenges in chip technology and computer hardware/ architectures will be highlighted.

https://cas.polito.it/LATS2024/program/keynotes

In a collaborative effort led by the WP5 Compiler team, successfully organized an effective 5-day Hackathon in Cambridge at the start of April 2024. The main focus was to speed up and foster collaboration among the WP5 members, affiliate partners from WP6 and external collaborators. More concretely:

• Knowledge exchange and integration of ZigZag/Stream within xDSL, processing linear algebra kernels (matmul, conv, etc.).
• Expansion of low-level abstractions with support dialects within xDSL for accelerator configuration (Snitch and SNAX).
• Establishing precise metrics for evaluating Snitch accelerator utilization (FPU occupancy, etc.)  from the cycle-accurate simulation framework.
• Expanding support of IREE to ingest CONVOLVE DNNs, either to linear algebra or to LLVM.
• Expanding support for xDSL’s ONNX frontend and lowering to linear algebra.
• Growing understanding of the memory allocation tasks and initial steps for the bufferization of CONVOLVE kernels.

This was the fourth plenary meeting, hosted by our Greek partner, the Institute of Communication and Computer Systems (ICCS) in Athens (see https://www.ece.ntua.gr/en/iccs). In particular, Dimitrios Soudris assisted by Sotirios Xydis did an excellent job in taking care of all local arrangements and showing great hospitality.

The meeting was for two full days, with a focus on the intermediate point demonstrations planned for the mid-term review. On the first day and the morning of the second day, the progress update and the status of the point demonstrations in different packages (WP) were presented. Each work package leader presented a short WP overview followed by about 15 minutes for each of the 16 point-demos, ending with an overall WP discussion. This allowed for in-depth treatment, typically with many questions raised. In addition, we spend time on our so-called Moon-Shot demo, a demonstrator integrating many of the results of the first half of the project. In particular, several Neural-Network accelerators will be included in the Moon-Shot tape-out using G22nm technology. Time is pressing, but we are still on schedule.

In the afternoon of the second day, we organized two parallel breakout tracks, with six different interactive sessions organised by different partners: 1) System-on-chip level modelling design space exploration and simulation (KU Leuven); 2) Hardware security (NXP Semiconductors); 3) Compute in memory (TU Delft); 4) Hardware learning for SNNs and ANNs (Manchester University); 5) Code generation (University of Edinburgh); and 6) Dynamic neural networks: models and hardware (International University of Rabat). We had good interactive sessions, and the main conclusions and action points from the sessions were summarized at the end of the plenary meeting.

Apart from the technical part, our hosts included dinners in top restaurants in the centre of Athens, one even with a direct view of the Acropolis. In addition, we had a nice tour of the Acropolis Museum on the second day. All amazing, thanks to our hosts. All participants agreed that these physical meetings are extremely important for the success of CONVOLVE; having two full days offers ample discussion time, including time for networking with other partners, and enjoying historic Athens.

We held this workshop to train project partners in using GVSoC to simulate PULP-based SoCs and as developers for new GVSoC simulation modules like accelerators, cores, and any other silicon design IP. We prepared several examples, extensive documentation, and end-to-end tutorials, which give a thorough insight into our simulator’s infrastructure. All of the material is publicly available on GitHub.

The third CONVOLVE plenary meeting was hosted by our partner Bosch at their research campus in Renningen. The first day of the 2-day meeting consisted of the presentation of all the work packages (WP). Four different applications were presented by our industrial partners in WP1, and WP2-6 presented the progress update on different tasks followed by a plan for intermediate demos for mid-year evaluation by the EC project officer.

The first day of the 2-day meeting consisted of the presentation of all the work packages (WP). Four different applications were presented by our industrial partners in WP1, and WP2-6 presented the progress update on different tasks followed by a plan for intermediate demos for mid-year evaluation by the EC project officer. The WP presentations were followed by feedback from our Industry Advisory Board (IAB). The main feedback of IAB was to make sure sufficient time is included in the plan for the final integration of different deliverables from the partners and to define their KPIs with respect to references. Also, there was a recommendation to think about commercialization of the proposed solutions in the longer term.

The second day was dedicated to two parallel breakout sessions with six different interactive sessions organized by different partners: 1) System on-chip level modeling design space exploration and simulation (KU Leuven), 2) Hardware security (NXP Semiconductors), 3) Compute in memory (TU Delft), 4) Hardware learning for SNNs and ANNs (Manchester University), 5) Code generation (University of Edinburgh) and 6) Dynamic neural networks: models and hardware (International University of Rabat). We had good interactive sessions, and the main conclusions and action points from the sessions were summarized at the end of the plenary meeting.

The CONVOLVE consortium met in Leuven, hosted by Katholieke Universiteit Leuven to have in-depth technical discussions and develop a roadmap of different activities. The technical meeting was organized following the two-step development approach proposed by CONVOLVE. The main goal of this meeting was to have discussions on the technical roadmaps and align the timelines of the different activities, their dependencies, and who will do what.

During the event, different tutorial sessions were organized where each partner presented their tools, research methodology, and future research directions. There were breakout sessions organized for each work package where special attention was given to deriving functional and non-functional requirements from the CONVOLVE use cases and making sure that the research activities would fit the ambitious CONVOLVE objectives.