EVENTS

The CONVOLVE project was proud to be represented at the Emerging Tech Conference on Edge Intelligence (ETCEI 2025), hosted at the University of West Attica Campus in Athens.

Organised by the Hellenic Emerging Technologies Industry Association (HETiA), University of West Attica (UWA), National and Kapodistrian University of Athens (UoA), and National Technical University of Athens (NTUA), ETCEI has become Greece’s premier forum for sharing the latest advances in Artificial Intelligence (AI), Edge Computing, and Intelligent Systems.

The theme of the 2025 edition, “Empowering Europe’s Chips Ecosystem through Emerging Technologies,” brought together researchers, industry, and policymakers to discuss how Europe can strengthen its capabilities in semiconductors, AI, edge computing, and digital sovereignty.

CONVOLVE’s participation was led by our partner ICCS/NTUA, who presented project perspectives and engaged with stakeholders on the role of AI and edge intelligence in shaping Europe’s future technological landscape.

This event offered a valuable opportunity for CONVOLVE to connect with the wider research and innovation community, and to contribute to ongoing discussions around next-generation computing systems that align with Europe’s strategic goals.

We are proud to share that Prof. Henk Corporaal (TU Eindhoven) delivered an invited talk at the OSSMPIC workshop at DATE 2025, in Lyon, presenting key results from the CONVOLVE project. His talk, titled “CGRAs for the Edge: Balancing Compute Efficiency and Flexibility,” explored the growing demand for adaptable, energy-efficient computing solutions at the edge—driven by advances in AI and signal processing.

A central focus of the presentation was the open-source R-Blocks CGRA chip, developed within CONVOLVE. Prof. Corporaal highlighted how this coarse-grain reconfigurable architecture demonstrates a promising balance between performance, flexibility, and scalability, making it ideal for edge applications where energy and area are constrained but adaptability is crucial.

The talk also introduced a metric for assessing architectural flexibility, and addressed the design trade-offs involved in developing programmable, application-tuned CGRAs.

This presentation underscores CONVOLVE’s commitment to advancing open, efficient computing platforms for Europe’s digital future.

The paper “Insights into Interpreters, Compilers, and Optimizers for Neural Networks” was accepted after peer review at CODAI 2025, a workshop held as part of HIPEAC 2025. The paper was presented orally at HIPEAC on January 20, 2025. 

Congratulations to Shreya Alladi from Universidad de Murcia for winning the CODAI Workshop 2025 Best Paper Award for her submission “Insights into Interpreters, Compilers, and Optimizers for Neural Networks,” supervised by Prof. Alexandra Jimborean.

A well-deserved recognition of her dedication and innovative work!

The recording of the presentation is available to watch here.

Henk Corporaal presented the keynote “AI at the Edge: Hype or Hope?” at the 4th HWAccelerators and FIRE FPGA workshop, the fourth of a series of seminars bringing together GPU and FPGA practitioners, computer science and engineering experts, scientific computing experts, application owners and HPC providers.

Henk’s keynote we started with an overview of Deep Learning Models and Networks used today, then address the SOTA in Edge computing, and its trends and developments.

They discuss what is needed to really bring AI to the Edge, how to bridge this huge energy-efficiency gap. Improvements are needed at all levels of the design stack; perhaps even new neural computing paradigms.

They conclude by offering a glimpse into the future, exploring potential breakthroughs on the horizon.

The series is part of the FIRE symposia and is jointly organized by SURF and the Hardware Acceleration Network NL. The event featured a lineup of discussions centered around architectural innovations in HW accelerators, including presentations from industrial heavyweights such as AMD, as well as talks from innovative startups such as Axelera AI and developments in the open source domain. The workshop also featured keynote talks from Riken supercomputer center and TU/e on recent developments in processor architecture.

The first edition of REACH 2024 kicked off with a bang, bringing together industry and academic leaders to explore the cutting-edge of computer architectures, AI, compilers, and systems. The conversations were rich with practical challenges from industry and innovative ideas from academia—truly inspiring!

A highlight was the talk by Alexandra Jimboreaan on “Optimizing Code Layout: Enhancing Performance and Efficiency through Instruction Reordering.”

Alexandra shared groundbreaking work on compile-time analysis, software-hardware co-designs, and instruction reordering techniques. These innovations enable a wide range of optimizations, from boosting memory-level parallelism to improving energy efficiency, performance, and security.

The talk also emphasized the importance of the compiler-architecture relationship in achieving resilience to speculative side-channel attacks, making it a crucial area of focus for both researchers and industry professionals.

Said Hamdioui, head of Computer Engineering Laboratory at Delft University of Technology and co-founder and CEO of Cognitive-IC presented the keynote “Computation-in Memory for edge AI: Opportunities and Challenges” at the IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS 2024) in France.

This talk discussed today’s chip technology and computer hardware/architectures (which enable the design of ICT systems), and highlighted their limitations making them unsuitable to enable energy efficient solutions needed; not only to minimize the ICT’s electricity consumption and ensure the sustainability, but also to enable many emerging energy-constrained applications such as edge-AI. The talk will covered both the device as well as the architecture aspects.

Thereafter, the talk covered some future directions for energy efficient computing, while focusing on Computation-In-Memory (CIM) architecture using both memsitor devices as well as SRAMs, and inspired with the brain. The huge potential of CIM (in realizing over 100X improvement in terms of energy efficiency) will be illustrated based on some real case studies, supported by data measurement of chip prototypes. Aspects related to design, test and reliability of such brain-inspired CIM architectures will be discussed. Future challenges in chip technology and computer hardware/ architectures will be highlighted.

Said Hamdioui, head of Computer Engineering Laboratory at Delft University of Technology and co-founder and CEO of Cognitive-IC presented the keynote “Chip technology and computing: the need of new mind set to sustain the future” at the IEEE Latin-American Test Symposium (LATS24), in Brasil.

The talk provides the edge computing challenges CONVOLVE is addressing, shows the directions, and present some results. It discusses today’s chip technology and computer hardware/architectures (which enable the design of ICT systems), and highlights their limitations making them unsuitable to enable energy efficient solutions needed; not only to minimize the ICT’s electricity consumption and ensure the sustainability, but also to enable many emerging energy-constrained applications such as edge-AI.

The talk covers both the device as well as the architecture aspects. Thereafter, the talk covers some future directions for energy efficient computing that CONVOLVE addresses, while focusing on Computation-In-Memory (CIM) architecture using memsitor devices and inspired with the brain. The huge potential of CIM (in realizing over 100X improvement in terms of energy efficiency) is illustrated based on some real case studies, supported by data measurement of chip prototypes. Aspects related to design, test and reliability of such brain-inspired CIM architectures will be discussed. Future challenges in chip technology and computer hardware/ architectures will be highlighted.

https://cas.polito.it/LATS2024/program/keynotes

CONVOLVE participated in the 2024 Design Automation Conference in San Francisco (DAC24). This special session aimed to discuss various approaches to neuromorphic computing for edge AI applications focusing on emerging technologies, novel architectures and sensing modalities to enhance perception.

These talks are related to four European projects funded under the same call entitled “Ultra-low-power, secure processors for edge computing”. These projects aiming at reducing by two orders of magnitude current energy consumptions and with budgets between 8 and 10 million Euros gather a large number of academic and industrial key European players on computing technologies.

Said Hamdioui of Delft University of Technology presented the tutorial overview “Chip technology and computing for Edge-AI devices: the need of new mind set to sustain the future” and discussed today’s chip technology and computer hardware/architectures for Neuromorphic Processing, and highlights their limitations, making them unsuitable to enable many emerging/evolving energy-constrained applications such as edge-AI. The talk covered both the device as well as the architecture aspects. Thereafter, the talk will covered an overview of the different alternative architectures being explored in the research community to address these limitations, both those using CMOS as well as those using post-CMOS devices. Finally, the talk showed future directions for energy efficient neuromorphic computing and links to the upcoming four presentations in the session.

Henk Corporaal of the Eindhoven University of Technology presented his talk on “Achieving PetaOps/W edge-AI processing”. With the rise of DL, our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. These SoCs need to support high throughput and energy-efficient processing, with a short time to market and at least 100 times more energy-efficient while offering sufficient flexibility and scalability. Since the design space is huge, advanced
tooling and a holistic approach with innovations at all levels of the design hierarchy is needed. Starting with an overview of SoA DL processing support and our methodology, this presentation covers several design choices impacting the energy efficiency and flexibility of DL hardware.

The Convolve project is in its final year. We had a very successful plenary meeting on February 27-28, 2025. It was hosted by our partners of the University of Murcia.   

On the first day all WP (work-package) leaders presented the status, results, plans and action points, for each work-package.  In particular attention was payed to the 2 moonshot demos (one Chip with tapeout, and one FPGA version) and the point demos to be demonstrated near the end of the project.

The second day we had in-depth breakout meetings (6 meetings in 2 parallel sessions), where those topics requiring more in-depth discussions were treated. All these meetings resulted in action points for the coming period.

Part of the meeting was a social event on Thursday evening, starting with a walk trough the nice city center of Murcia, and ending with a very good diner in a nice restaurant. We can look back at a very fruitful meeting with many lively discussions, largely thanks to the organization and great hospitality of our hosts Alexandra and Alberto.

This was the fourth plenary meeting, hosted by our Greek partner, the Institute of Communication and Computer Systems (ICCS) in Athens (see https://www.ece.ntua.gr/en/iccs). In particular, Dimitrios Soudris assisted by Sotirios Xydis did an excellent job in taking care of all local arrangements and showing great hospitality.

The meeting was for two full days, with a focus on the intermediate point demonstrations planned for the mid-term review. On the first day and the morning of the second day, the progress update and the status of the point demonstrations in different packages (WP) were presented. Each work package leader presented a short WP overview followed by about 15 minutes for each of the 16 point-demos, ending with an overall WP discussion. This allowed for in-depth treatment, typically with many questions raised. In addition, we spend time on our so-called Moon-Shot demo, a demonstrator integrating many of the results of the first half of the project. In particular, several Neural-Network accelerators will be included in the Moon-Shot tape-out using G22nm technology. Time is pressing, but we are still on schedule.

In the afternoon of the second day, we organized two parallel breakout tracks, with six different interactive sessions organised by different partners: 1) System-on-chip level modelling design space exploration and simulation (KU Leuven); 2) Hardware security (NXP Semiconductors); 3) Compute in memory (TU Delft); 4) Hardware learning for SNNs and ANNs (Manchester University); 5) Code generation (University of Edinburgh); and 6) Dynamic neural networks: models and hardware (International University of Rabat). We had good interactive sessions, and the main conclusions and action points from the sessions were summarized at the end of the plenary meeting.

Apart from the technical part, our hosts included dinners in top restaurants in the centre of Athens, one even with a direct view of the Acropolis. In addition, we had a nice tour of the Acropolis Museum on the second day. All amazing, thanks to our hosts. All participants agreed that these physical meetings are extremely important for the success of CONVOLVE; having two full days offers ample discussion time, including time for networking with other partners, and enjoying historic Athens.

The third CONVOLVE plenary meeting was hosted by our partner Bosch at their research campus in Renningen. The first day of the 2-day meeting consisted of the presentation of all the work packages (WP). Four different applications were presented by our industrial partners in WP1, and WP2-6 presented the progress update on different tasks followed by a plan for intermediate demos for mid-year evaluation by the EC project officer.

The first day of the 2-day meeting consisted of the presentation of all the work packages (WP). Four different applications were presented by our industrial partners in WP1, and WP2-6 presented the progress update on different tasks followed by a plan for intermediate demos for mid-year evaluation by the EC project officer. The WP presentations were followed by feedback from our Industry Advisory Board (IAB). The main feedback of IAB was to make sure sufficient time is included in the plan for the final integration of different deliverables from the partners and to define their KPIs with respect to references. Also, there was a recommendation to think about commercialization of the proposed solutions in the longer term.

The second day was dedicated to two parallel breakout sessions with six different interactive sessions organized by different partners: 1) System on-chip level modeling design space exploration and simulation (KU Leuven), 2) Hardware security (NXP Semiconductors), 3) Compute in memory (TU Delft), 4) Hardware learning for SNNs and ANNs (Manchester University), 5) Code generation (University of Edinburgh) and 6) Dynamic neural networks: models and hardware (International University of Rabat). We had good interactive sessions, and the main conclusions and action points from the sessions were summarized at the end of the plenary meeting.