EVENTS

The CONVOLVE project was presented at the Design, Automation and Test in Europe Conference (DATE) 2026.

In the session “From Physical Tamper Detection to AI-Assisted Trust Verification”, Adrian Marotzke (NXP Semiconductors) presented the paper “The PMP Snapshot Engine: Fast and Fault-Resilient PMP Reconfiguration for RISC-V”, highlighting results from CONVOLVE’s work on secure and efficient edge computing.

The contribution, developed in collaboration between TU Delft, NXP, and King Abdulaziz City for Science and Technology, demonstrates a lightweight hardware extension for fast and fault-resilient PMP reconfiguration in RISC-V systems.

Participation in DATE 2026 enabled engagement with the hardware and systems community and dissemination of CONVOLVE’s latest results in secure edge-AI technologies.

A presentation was delivered by Thomas Verelst at the Leuven Data Science Meetup, focusing on research related to model compression within the CONVOLVE project.

The 30-minute talk introduced approaches to efficient neural network design, including pruning techniques and dynamic neural networks. It highlighted how these methods can reduce computational requirements while maintaining model performance, supporting more efficient deployment of AI systems. The session provided insights into practical strategies for optimising AI models, contributing to discussions on scalable and resource-efficient machine learning.

The event engaged both the research community and a broader audience, supporting knowledge exchange and raising awareness of developments in efficient AI and model optimisation.

More information: https://www.meetup.com/data-science-leuven/events/311853177/?eventOrigin=group_past_events

The KU Leuven Semiconductor School hosted a summer school on edge AI hardware, targeting Brazilian students as part of international outreach and training activities.

The programme introduced participants to key concepts in AI accelerator design and hardware-efficient machine learning, with a focus on innovations relevant to edge AI systems. Topics included approaches to improving performance and energy efficiency through specialised hardware architectures, as well as design methodologies supporting efficient deployment of AI at the edge.

The activity contributed to CONVOLVE’s dissemination and capacity-building efforts, supporting knowledge exchange beyond Europe and engaging emerging researchers with current developments in AI hardware and semiconductor technologies.

More information: https://eng.kuleuven.be/nieuws-en-agenda/evenementen/semiconductor-school

Alexandra Jimborean (University of Murcia) delivered an invited talk at the Workshop on Co-evolution of Algorithms, Compilers, and Hardware for Performance 2026, part of the FASTCode workshop series and co-located with PPoPP 2026.

Her presentation, “Optimizing for the Edge: From Neural Compilation to Instruction Fusion in RISC-V Systems,” addressed compiler and hardware co-design approaches for improving performance and efficiency in edge AI systems. The talk covered neural compilation, instruction fusion, and optimisation techniques for RISC-V-based platforms.

The workshop brought together researchers and industry participants working on cross-layer optimisation across algorithms, compilers, and hardware for next-generation computing systems.

More information: https://fastcode.org/events/coevolution-workshop/

An invited talk was delivered by Alexandra Jimborean (Umeå University) at the National University of Singapore.

The presentation, titled “Optimizing for the Edge: From Neural Compilation to Instruction Fusion in RISC-V Systems,” explored approaches to improving performance and efficiency in edge computing systems. It focused on compilation techniques for RISC-V platforms, highlighting strategies such as neural compilation and instruction fusion to optimise execution.

The talk addressed how coordinated optimisation across algorithms, compilers, and hardware can enhance performance while maintaining energy efficiency, particularly for AI workloads deployed at the edge. The activity contributed to international scientific exchange, engaging the research community and supporting collaboration on compiler technologies and efficient computing systems aligned with CONVOLVE objectives.

More information: https://events.comp.nus.edu.sg/view/25512

The CONVOLVE project was proud to be represented at the Emerging Tech Conference on Edge Intelligence (ETCEI 2025), hosted at the University of West Attica Campus in Athens.

Organised by the Hellenic Emerging Technologies Industry Association (HETiA), University of West Attica (UWA), National and Kapodistrian University of Athens (UoA), and National Technical University of Athens (NTUA), ETCEI has become Greece’s premier forum for sharing the latest advances in Artificial Intelligence (AI), Edge Computing, and Intelligent Systems.

The theme of the 2025 edition, “Empowering Europe’s Chips Ecosystem through Emerging Technologies,” brought together researchers, industry, and policymakers to discuss how Europe can strengthen its capabilities in semiconductors, AI, edge computing, and digital sovereignty.

CONVOLVE’s participation was led by our partner ICCS/NTUA, who presented project perspectives and engaged with stakeholders on the role of AI and edge intelligence in shaping Europe’s future technological landscape.

This event offered a valuable opportunity for CONVOLVE to connect with the wider research and innovation community, and to contribute to ongoing discussions around next-generation computing systems that align with Europe’s strategic goals.

The 2025 MLIR (Un)School brought together researchers, industry practitioners, and innovators to explore advanced topics in compiler infrastructure based on the Multi-Level Intermediate Representation (MLIR).

The programme focused on modern compiler design and extensible infrastructures, with sessions covering domain-specific languages, intermediate representations, and optimisation techniques for heterogeneous systems. Participants engaged with both conceptual and practical aspects of MLIR, including its applications in AI, high-performance computing, and emerging hardware platforms.

The event provided a collaborative environment for knowledge exchange across academia and industry, supporting the development of flexible and efficient software toolchains. It also contributed to advancing expertise in compiler technologies relevant to CONVOLVE objectives.

More information: https://mlir-school.github.io/summer-2025/

A talk by Marian Verhelst (KU Leuven) was presented at the W1 workshop on “Energy-Efficient Hardware Accelerators for Edge AI and Data-Intensive Applications” during the ESSERC 2025.

The presentation explored decoupled dataflow accelerator design, an approach that separates key components of the hardware stack—dataflow, scheduling, and memory layout—so they can be optimized independently. This enables more flexible adaptation to the diverse requirements of AI workloads while improving overall efficiency.

The talk introduced automated design flows for generating key hardware building blocks, including Multiply-Accumulate (MAC) arrays for high-performance computation and streaming architectures for efficient data movement. It also highlighted automated data layout transformations to optimise memory organisation, reduce latency, and improve bandwidth utilisation.

These components are integrated through a customised compiler, enabling the seamless translation of AI models into hardware configurations tailored for performance and energy efficiency. The approach supports the development of scalable, energy-efficient accelerator architectures for next-generation edge AI systems.

At DATE 2025 (Design, Automation and Test in Europe) in Lyon, the CONVOLVE project highlighted two complementary aspects of its work on next-generation edge-AI processors: security-by-design and reconfigurable compute architectures for energy-efficient edge computing.

In the DATE Multi-Partner Project track, CONVOLVE presented a talk and interactive poster session on the security architecture of the CONVOLVE chip. The contribution addressed hardware-level defences against physical attacks, protection of AI models and intellectual property, and the integration of security-by-design principles in ultra-low-power edge-AI processors.

The presentation, “Multi-Partner Project: Securing Future Edge-AI Processors in Practice”, was delivered by Sven Argo (Ruhr University Bochum) in collaboration with project partners.

CONVOLVE was also featured in the OSSMPIC workshop at DATE 2025, where Prof. Henk Corporaal (TU Eindhoven) gave an invited talk on coarse-grain reconfigurable architectures (CGRAs) for edge workloads.

The presentation highlighted progress on the open-source R-Blocks CGRA chip developed within CONVOLVE, focusing on programmability and adaptability under tight energy and area constraints.

The ASPLOS 2025 xDSL Workshop brought together researchers and developers to explore advances in compiler technologies and domain-specific languages (DSLs) within modern computing systems.

The workshop focused on the xDSL framework as a flexible infrastructure for building and extending compilers. Discussions covered the design and implementation of DSLs, as well as techniques for optimising code generation and targeting heterogeneous hardware platforms. Particular attention was given to how compiler frameworks can support efficient execution across diverse architectures, including those used in AI and high-performance computing. The event provided a platform for exchanging ideas on improving programmability and performance through modular and extensible compiler design.

The activity contributed to knowledge exchange within the research community, supporting developments in compiler technologies relevant to CONVOLVE objectives.

More information: https://xdsl.dev/events/2025-ASPLOS/

An invited lecture by Marian Verhelst (KU Leuven) was delivered at ETH Zurich within a research seminar hosted by the Computer Architecture and Systems Lab (HTOR group).

The lecture presented advances in edge AI hardware acceleration, including work connected to the CONVOLVE project. It focused on mapping AI workloads onto specialised hardware accelerators, highlighting approaches to improve performance and energy efficiency through hardware–software co-design. Key topics included design strategies for adapting neural network models to accelerator architectures, as well as techniques to balance throughput, latency, and power consumption in edge environments. The session contributed to ongoing research discussions on efficient AI processing and next-generation accelerator design.

The lecture engaged the academic research community and supported knowledge exchange on emerging approaches to AI accelerator optimisation and deployment.

The HiPEAC 2025 xDSL Workshop brought together researchers and practitioners to explore advances in compiler technologies and domain-specific languages (DSLs).

The workshop focused on the xDSL framework, highlighting its role in enabling flexible and extensible compiler infrastructures for modern computing systems. Sessions covered approaches to designing and implementing DSLs, as well as techniques for optimising code generation and supporting heterogeneous hardware architectures. The event provided a platform for discussing how compiler innovations can improve the development and deployment of efficient software stacks, particularly in the context of emerging AI and high-performance computing workloads.

The activity contributed to knowledge exchange within the research community, supporting developments in compiler design and optimisation frameworks relevant to CONVOLVE objectives.

More information: https://xdsl.dev/events/2025-HiPEAC/

The MLIR Winter School 2025 brought together researchers, developers, and innovators to explore advances in compiler infrastructure based on the Multi-Level Intermediate Representation (MLIR).

The programme covered key concepts in modern compiler design, focusing on modular and extensible infrastructures for building domain-specific compilers. Sessions addressed techniques for representing and optimising computations across multiple abstraction levels, supporting efficient execution on heterogeneous hardware systems. Participants engaged with both theoretical foundations and practical applications of MLIR, including its use in AI, high-performance computing, and emerging hardware architectures. The event provided a platform for knowledge exchange on improving programmability and performance through advanced compiler frameworks.

The activity contributed to strengthening expertise in compiler technologies and optimisation, supporting CONVOLVE objectives related to software toolchains and efficient computing systems.

More information: https://sites.google.com/view/mlirwinterschoolparis2025/home

The paper “Insights into Interpreters, Compilers, and Optimizers for Neural Networks” was accepted after peer review at CODAI 2025, a workshop held as part of HIPEAC 2025. The paper was presented orally at HIPEAC on January 20, 2025. 

Congratulations to Shreya Alladi from Universidad de Murcia for winning the CODAI Workshop 2025 Best Paper Award for her submission “Insights into Interpreters, Compilers, and Optimizers for Neural Networks,” supervised by Prof. Alexandra Jimborean.

A well-deserved recognition of her dedication and innovative work!

The recording of the presentation is available to watch here.

Henk Corporaal presented the keynote “AI at the Edge: Hype or Hope?” at the 4th HWAccelerators and FIRE FPGA workshop, the fourth of a series of seminars bringing together GPU and FPGA practitioners, computer science and engineering experts, scientific computing experts, application owners and HPC providers.

Henk’s keynote we started with an overview of Deep Learning Models and Networks used today, then address the SOTA in Edge computing, and its trends and developments.

They discuss what is needed to really bring AI to the Edge, how to bridge this huge energy-efficiency gap. Improvements are needed at all levels of the design stack; perhaps even new neural computing paradigms.

They conclude by offering a glimpse into the future, exploring potential breakthroughs on the horizon.

The series is part of the FIRE symposia and is jointly organized by SURF and the Hardware Acceleration Network NL. The event featured a lineup of discussions centered around architectural innovations in HW accelerators, including presentations from industrial heavyweights such as AMD, as well as talks from innovative startups such as Axelera AI and developments in the open source domain. The workshop also featured keynote talks from Riken supercomputer center and TU/e on recent developments in processor architecture.

The first edition of REACH 2024 kicked off with a bang, bringing together industry and academic leaders to explore the cutting-edge of computer architectures, AI, compilers, and systems. The conversations were rich with practical challenges from industry and innovative ideas from academia—truly inspiring!

A highlight was the talk by Alexandra Jimboreaan on “Optimizing Code Layout: Enhancing Performance and Efficiency through Instruction Reordering.”

Alexandra shared groundbreaking work on compile-time analysis, software-hardware co-designs, and instruction reordering techniques. These innovations enable a wide range of optimizations, from boosting memory-level parallelism to improving energy efficiency, performance, and security.

The talk also emphasized the importance of the compiler-architecture relationship in achieving resilience to speculative side-channel attacks, making it a crucial area of focus for both researchers and industry professionals.

Said Hamdioui, head of Computer Engineering Laboratory at Delft University of Technology and co-founder and CEO of Cognitive-IC presented the keynote “Computation-in Memory for edge AI: Opportunities and Challenges” at the IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS 2024) in France.

This talk discussed today’s chip technology and computer hardware/architectures (which enable the design of ICT systems), and highlighted their limitations making them unsuitable to enable energy efficient solutions needed; not only to minimize the ICT’s electricity consumption and ensure the sustainability, but also to enable many emerging energy-constrained applications such as edge-AI. The talk will covered both the device as well as the architecture aspects.

Thereafter, the talk covered some future directions for energy efficient computing, while focusing on Computation-In-Memory (CIM) architecture using both memsitor devices as well as SRAMs, and inspired with the brain. The huge potential of CIM (in realizing over 100X improvement in terms of energy efficiency) will be illustrated based on some real case studies, supported by data measurement of chip prototypes. Aspects related to design, test and reliability of such brain-inspired CIM architectures will be discussed. Future challenges in chip technology and computer hardware/ architectures will be highlighted.

As part of the Tage der Genforschung outreach event, high school students took part in a hands-on workshop on brain-inspired computing. Guided by researchers, they built simple neuronal circuits using electronic “neurons,” gaining insight into how spiking neural networks function.

The workshop was supported by researchers from the Friedrich Miescher Institute for Biomedical Research (FMI), who helped design and deliver the activity. Their involvement enabled students to engage directly with current approaches in neuromorphic computing and experimental neuroscience.

The session introduced key concepts in an accessible, interactive way, allowing students to experiment with connectivity and observe how signals propagate through networks. It formed part of a broader programme showcasing developments in biomedical and computational science.

This outreach effort supports CONVOLVE’s commitment to dissemination and capacity building, fostering early interest in AI hardware and strengthening connections between research and education.

More information: https://zenkelab.org/2024/06/high-school-students-build-neuronal-circuits/

Said Hamdioui, head of Computer Engineering Laboratory at Delft University of Technology and co-founder and CEO of Cognitive-IC presented the keynote “Chip technology and computing: the need of new mind set to sustain the future” at the IEEE Latin-American Test Symposium (LATS24), in Brasil.

The talk provides the edge computing challenges CONVOLVE is addressing, shows the directions, and present some results. It discusses today’s chip technology and computer hardware/architectures (which enable the design of ICT systems), and highlights their limitations making them unsuitable to enable energy efficient solutions needed; not only to minimize the ICT’s electricity consumption and ensure the sustainability, but also to enable many emerging energy-constrained applications such as edge-AI.

The talk covers both the device as well as the architecture aspects. Thereafter, the talk covers some future directions for energy efficient computing that CONVOLVE addresses, while focusing on Computation-In-Memory (CIM) architecture using memsitor devices and inspired with the brain. The huge potential of CIM (in realizing over 100X improvement in terms of energy efficiency) is illustrated based on some real case studies, supported by data measurement of chip prototypes. Aspects related to design, test and reliability of such brain-inspired CIM architectures will be discussed. Future challenges in chip technology and computer hardware/ architectures will be highlighted.

https://cas.polito.it/LATS2024/program/keynotes

(KU Leuven) contributed to the MEAD Education online course on Hardware-Efficient Edge AI (12–22 March 2024), delivering four modules covering edge ML context, acceleration concepts, hardware-level optimisation (quantisation and sparsity), and cross-layer design.

The course provided participants with a structured overview of design space exploration, AI accelerator architectures, and hardware–software co-design, with a focus on enabling efficient machine learning at the edge. It targeted research and industry audiences, supporting knowledge transfer on emerging approaches to energy-efficient AI hardware design.

CONVOLVE participated in the 2024 Design Automation Conference in San Francisco (DAC24). This special session aimed to discuss various approaches to neuromorphic computing for edge AI applications focusing on emerging technologies, novel architectures and sensing modalities to enhance perception.

These talks are related to four European projects funded under the same call entitled “Ultra-low-power, secure processors for edge computing”. These projects aiming at reducing by two orders of magnitude current energy consumptions and with budgets between 8 and 10 million Euros gather a large number of academic and industrial key European players on computing technologies.

Said Hamdioui of Delft University of Technology presented the tutorial overview “Chip technology and computing for Edge-AI devices: the need of new mind set to sustain the future” and discussed today’s chip technology and computer hardware/architectures for Neuromorphic Processing, and highlights their limitations, making them unsuitable to enable many emerging/evolving energy-constrained applications such as edge-AI. The talk covered both the device as well as the architecture aspects. Thereafter, the talk will covered an overview of the different alternative architectures being explored in the research community to address these limitations, both those using CMOS as well as those using post-CMOS devices. Finally, the talk showed future directions for energy efficient neuromorphic computing and links to the upcoming four presentations in the session.

Henk Corporaal of the Eindhoven University of Technology presented his talk on “Achieving PetaOps/W edge-AI processing”. With the rise of DL, our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. These SoCs need to support high throughput and energy-efficient processing, with a short time to market and at least 100 times more energy-efficient while offering sufficient flexibility and scalability. Since the design space is huge, advanced
tooling and a holistic approach with innovations at all levels of the design hierarchy is needed. Starting with an overview of SoA DL processing support and our methodology, this presentation covers several design choices impacting the energy efficiency and flexibility of DL hardware.

The CONVOLVE consortium convened in Eindhoven for its Final Plenary Meeting, marking a key milestone as the project enters its final phase ahead of the review meeting.

Over two days, partners reviewed progress across all work packages, consolidated results, and aligned on final deliverables, demonstrations, and key performance indicators. The meeting focused on ensuring readiness for the final project review, including rehearsals of presentations and demos, and discussions on achievements, valorisation, and follow-up activities.

The programme also featured a keynote by Federico Corradi on the future of neuromorphic computing, providing a forward-looking perspective on energy-efficient AI and emerging hardware paradigms.

Beyond the technical sessions, the plenary provided an opportunity for in-person exchange and collaboration. Participants visited the historic NatLab, a landmark of innovation in Eindhoven, followed by a consortium dinner at De Oude Telefooncentrale. Located in a former Philips building at Strijp-S, the venue once housed the Eindhoven telephone exchange until 1978, offering a unique setting to reflect on both technological heritage and future innovation.

As CONVOLVE approaches its conclusion, the Final Plenary reinforced the project’s strong collaboration and its contributions to next-generation ultra-low-power, secure edge AI systems.

The Convolve project is in its final year. We had a very successful plenary meeting on February 27-28, 2025. It was hosted by our partners of the University of Murcia.   

On the first day all WP (work-package) leaders presented the status, results, plans and action points, for each work-package.  In particular attention was payed to the 2 moonshot demos (one Chip with tapeout, and one FPGA version) and the point demos to be demonstrated near the end of the project.

The second day we had in-depth breakout meetings (6 meetings in 2 parallel sessions), where those topics requiring more in-depth discussions were treated. All these meetings resulted in action points for the coming period.

Part of the meeting was a social event on Thursday evening, starting with a walk trough the nice city center of Murcia, and ending with a very good diner in a nice restaurant. We can look back at a very fruitful meeting with many lively discussions, largely thanks to the organization and great hospitality of our hosts Alexandra and Alberto.

This was the fourth plenary meeting, hosted by our Greek partner, the Institute of Communication and Computer Systems (ICCS) in Athens (see https://www.ece.ntua.gr/en/iccs). In particular, Dimitrios Soudris assisted by Sotirios Xydis did an excellent job in taking care of all local arrangements and showing great hospitality.

The meeting was for two full days, with a focus on the intermediate point demonstrations planned for the mid-term review. On the first day and the morning of the second day, the progress update and the status of the point demonstrations in different packages (WP) were presented. Each work package leader presented a short WP overview followed by about 15 minutes for each of the 16 point-demos, ending with an overall WP discussion. This allowed for in-depth treatment, typically with many questions raised. In addition, we spend time on our so-called Moon-Shot demo, a demonstrator integrating many of the results of the first half of the project. In particular, several Neural-Network accelerators will be included in the Moon-Shot tape-out using G22nm technology. Time is pressing, but we are still on schedule.

In the afternoon of the second day, we organized two parallel breakout tracks, with six different interactive sessions organised by different partners: 1) System-on-chip level modelling design space exploration and simulation (KU Leuven); 2) Hardware security (NXP Semiconductors); 3) Compute in memory (TU Delft); 4) Hardware learning for SNNs and ANNs (Manchester University); 5) Code generation (University of Edinburgh); and 6) Dynamic neural networks: models and hardware (International University of Rabat). We had good interactive sessions, and the main conclusions and action points from the sessions were summarized at the end of the plenary meeting.

Apart from the technical part, our hosts included dinners in top restaurants in the centre of Athens, one even with a direct view of the Acropolis. In addition, we had a nice tour of the Acropolis Museum on the second day. All amazing, thanks to our hosts. All participants agreed that these physical meetings are extremely important for the success of CONVOLVE; having two full days offers ample discussion time, including time for networking with other partners, and enjoying historic Athens.

The third CONVOLVE plenary meeting was hosted by our partner Bosch at their research campus in Renningen. The first day of the 2-day meeting consisted of the presentation of all the work packages (WP). Four different applications were presented by our industrial partners in WP1, and WP2-6 presented the progress update on different tasks followed by a plan for intermediate demos for mid-year evaluation by the EC project officer.

The first day of the 2-day meeting consisted of the presentation of all the work packages (WP). Four different applications were presented by our industrial partners in WP1, and WP2-6 presented the progress update on different tasks followed by a plan for intermediate demos for mid-year evaluation by the EC project officer. The WP presentations were followed by feedback from our Industry Advisory Board (IAB). The main feedback of IAB was to make sure sufficient time is included in the plan for the final integration of different deliverables from the partners and to define their KPIs with respect to references. Also, there was a recommendation to think about commercialization of the proposed solutions in the longer term.

The second day was dedicated to two parallel breakout sessions with six different interactive sessions organized by different partners: 1) System on-chip level modeling design space exploration and simulation (KU Leuven), 2) Hardware security (NXP Semiconductors), 3) Compute in memory (TU Delft), 4) Hardware learning for SNNs and ANNs (Manchester University), 5) Code generation (University of Edinburgh) and 6) Dynamic neural networks: models and hardware (International University of Rabat). We had good interactive sessions, and the main conclusions and action points from the sessions were summarized at the end of the plenary meeting.